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| GS4915 ClockCleanerTM GS4915 Data Sheet Key Features * Reduces jitter for clocks of 148.5MHz, 148.5/1.001MHz, 74.25MHz, 74.25/1.001MHz and 27MHz Output jitter as low as 20ps peak to peak Automatic bypass mode for all other clock rates Loop bandwidth adjustable as low as 2kHz Output skew control Input selectable as differential or single-ended Both single-ended and differential outputs Uses the GO1555 VCO Small 6mm x 6mm 40-pin QFN package Pb-free and RoHS compliant Description The GS4915 provides a low jitter clock output when fed with an HD or SD video clock input. Other input clock frequencies between 12MHz and 165MHz can be automatically passed through to the GS4915 outputs. An internal 2:1 mux allows the user to select between a differential or single-ended (LVCMOS) input clock. Both a single-ended LVCMOS- compatible and an LVDS-compatible differential output are provided. The GS4915 may operate in either auto or fixed frequency mode. In auto mode, the device will automatically clean the selected input clock if its frequency is found to be one of the supported SD or HD clock rates. In fixed mode, the user selects only one of these frequencies to be cleaned. In addition, the device allows the user to select between auto or manual bypass operation. In autobypass mode, the GS4915 will automatically bypass its cleaning stage and pass the input clock signal directly to the output whenever the device is unlocked, which includes the case where the input frequency is something other than the five frequencies supported. In manual bypass mode, the input signal passes through directly to the output. The GS4915 can optionally double the output frequency for 74.25MHz or 74.175MHz HD clocks in order to provide optimal jitter performance of some serializers. The GS4915 also provides the user with a 2-state skew control. The output clocks produced by the device may be advanced by 1/4 of an output CLK period in order to accommodate downstream setup and hold requirements. The GS4915 is designed to operate with the GO1555 VCO. The GS4915 Clock Cleaner complements Gennum's GS4911B Clock and Timing Generator for implementing a video genlock solution. Whereas the GS4911B itself cleans low-frequency jitter, the GS4915 is designed to clean primarily the higher frequency jitter of clocks generated by the GS4911B. * * * * * * * * * Applications High definition video systems. Digital video recording, playback, processing and display devices. 39145 - 3 November 2007 1 of 26 www.gennum.com GS4915 Data Sheet Functional Block Diagram VCO_VDD REG_VDD CP_VDD LF CP_RES 2.5V Regulator CLKIN CLKIN DIFF I/P Buffer 0 1 CLKIN_SE S-E I/P Buffer Clock Cleaning PLL Skew Select Phase Detector Charge Pump VCO Receiver Divide by N VCO VCO DIFF O/P Buffer clkout clkin 0 1 S-E O/P Buffer CLKOUT CLKOUT IPSEL CLKOUT_SE Frequency Detection Digital Control Block bypass RESET SKEW_EN AUTOBYPASS FCTRL[1:0] BYPASS GS4915 Functional Block Diagram 39145 - 3 November 2007 DOUBLE LOCK 2 of 26 GS4915 Data Sheet Contents Key Features .................................................................................................................1 Applications...................................................................................................................1 Description ....................................................................................................................1 Functional Block Diagram .............................................................................................2 1. Pin Out ......................................................................................................................4 1.1 Pin Assignment ...............................................................................................4 1.2 Pin Descriptions ..............................................................................................5 2. Electrical Characteristics ...........................................................................................8 2.1 Absolute Maximum Ratings ............................................................................8 2.2 DC Electrical Characteristics ..........................................................................8 2.3 AC Electrical Characteristics .........................................................................10 2.4 Solder Reflow Profiles ...................................................................................11 3. Detailed Description ................................................................................................12 3.1 Functional Overview .....................................................................................12 3.2 Clock Inputs ..................................................................................................12 3.2.1 Differential Clock Input.........................................................................13 3.2.2 Single-Ended Clock Input ....................................................................13 3.2.3 Input Clock Selection ...........................................................................13 3.2.4 Unused Clock Inputs............................................................................13 3.3 Clock Cleaning PLL ......................................................................................13 3.3.1 Phase Detector ....................................................................................14 3.3.2 Charge Pump.......................................................................................14 3.3.3 Loop Filter ............................................................................................14 3.3.4 External VCO.......................................................................................15 3.4 Modes of Operation ......................................................................................15 3.4.1 Frequency Modes ................................................................................15 3.4.2 Bypass Modes .....................................................................................17 3.5 Output Clock Frequency and Jitter ...............................................................18 3.6 Output Skew .................................................................................................20 3.7 Clock Outputs ...............................................................................................21 3.7.1 Differential Clock Output ......................................................................21 3.7.2 Single-Ended Clock Output .................................................................21 3.8 Device Reset .................................................................................................21 3.8.1 Hardware Reset ...................................................................................21 4. Typical Application Circuit .......................................................................................22 5. References & Relevant Standards ..........................................................................23 6. Package & Ordering Information .............................................................................24 6.1 Package Dimensions ....................................................................................24 6.2 Recommended PCB Footprint ......................................................................25 6.3 Packaging Data .............................................................................................25 6.4 Ordering Information .....................................................................................25 7. Revision History ......................................................................................................26 39145 - 3 November 2007 3 of 26 GS4915 Data Sheet 1. Pin Out 1.1 Pin Assignment VCO_ GND VCO_ VDD DIV_VDD 32 CP_ VDD CP_ RES AGND 40 39 38 37 36 35 34 33 31 30 29 28 27 REG _VDD AGND PD _VDD CLKIN CLKIN AGND IN_VDD CLKIN_ SE AGND RESET AGND VCO VCO LF 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 AGND CLKOUT CLKOUT DIFF _OUT_ VDD AGND D _VDD CLKOUT_ SE SE _ VDD GND LOCK GS4915 40-pin QFN (Top View ) 26 25 24 23 22 21 IPSEL SKEW _EN D_ VDD FCTRL0 F CTRL1 AUTOBYPASS DOUBLE BYPASS GND GND Ground Pad (Bottom of Package) Figure 1-1: 40-Pin QFN 39145 - 3 November 2007 4 of 26 GS4915 Data Sheet 1.2 Pin Descriptions Table 1-1: Pin Descriptions Pin Number 1 2, 6, 9, 26, 30, 31, 40 3 4, 5 Name REG_VDD AGND PD_VDD CLKIN, CLKIN Timing - - - - Type Power Power Power Input Description Positive power supply connection for the internal voltage regulator. Connect to filtered +3.3V DC. Ground connection for analog blocks and IO's. Connect to clean analog GND. Positive power supply connection for the phase detector. Connect to filtered +1.8V DC. CLOCK SIGNAL INPUTS Signal levels are CML/LVDS compatible. A differential clock input signal is applied to these pins. 7 8 IN_VDD CLKIN_SE - - Power Input Positive power supply connection for the single-ended and differential input clock buffers. Supplies CLKIN_SE. Connect to filtered +1.8V DC. CLOCK SIGNAL INPUT Signal levels are LVCMOS compatible. A single-ended video clock input signal is applied to this pin. 10 RESET Non synchronous Input CONTROL SIGNAL INPUT Signal levels are LVCMOS/LVTTL compatible. See Section 3.8.1 for operation. 11 IPSEL Non synchronous Input CONTROL SIGNAL INPUT Signal levels are LVCMOS compatible. Selects which input clock is cleaned by the device. See Section 3.2.3 for operation. 12, 20, 22 13 GND BYPASS - Non synchronous Power Input Ground connection for digital blocks and IO's. Connect to GND. CONTROL SIGNAL INPUT Signal levels are LVCMOS compatible. See Manual Bypass Section 3.4.2. 14 AUTOBYPASS Non synchronous Input CONTROL SIGNAL INPUT Signal levels are LVCMOS compatible. Selects the bypass mode of the device. See Manual Bypass Section 3.4.2. 15 17, 16 D_VDD FCTRL1, FCTRL0 - Non synchronous Power Input Positive power supply connection for digital block. Connect to filtered +1.8V DC. The digital block includes pins 10 - 21. CONTROL SIGNAL INPUTS Signal levels are LVCMOS compatible. Selects the frequency mode of the device. See Section 3.4.1 for operation. 39145 - 3 November 2007 5 of 26 GS4915 Data Sheet Table 1-1: Pin Descriptions (Continued) Pin Number 18 Name DOUBLE Timing Non synchronous Type Input Description CONTROL SIGNAL INPUT Signal levels are LVCMOS compatible. Controls the output frequency of the cleaned clock, for HD input clocks. See Section 3.5 for operation. 19 SKEW_EN Non synchronous Input CONTROL SIGNAL INPUT Signal levels are LVCMOS compatible. Selects the phase of the output clock with respect to the selected input clock. See Section 3.6 for operation. 21 LOCK Non synchronous Output STATUS SIGNAL OUTPUT Signal levels are LVCMOS compatible. This pin will be HIGH when the output clock is locked to the selected input clock. It will be LOW otherwise. 23 SE_VDD - Power Positive power supply connection for the single-ended clock driver. Determines the output level of CLKOUT_SE. Connect to filtered +1.8V DC or +3.3V DC. NOTE: If the single-ended clock output is not used, this pin should be tied to ground. 24 CLKOUT_SE - Output CLOCK SIGNAL OUTPUT Signal levels are LVCMOS compatible. Single-ended video clock output signal. See Section 3.7.2 for operation. 25 D_VDD - Power Positive power supply connection for the single-ended output clock buffer. Connect to filtered +1.8V DC. NOTE: If the single-ended clock output is not used, this pin should be tied to ground. 27 DIFF_OUT_VDD - Power Positive power supply connection for the LVDS clock outputs. Connect to filtered +1.8V DC. NOTE: If the LVDS clock outputs are not used, this pin should be tied to ground. 29, 28 CLKOUT, CLKOUT - Output CLOCK SIGNAL OUTPUT Differential video clock output signal. This is the lowest jitter output of the device. See Section 3.7.1 for operation. 32 33,34 DIV_VDD VCO, VCO - Analog Power Input Positive power supply connection for the divider block. Connect to filtered +1.8V DC. Differential input for the external VCO reference signal. When using the recommended VCO, leave VCO unconnected. See Section 3.3.4 for operation. 35 VCO_GND - Power Ground reference for the external voltage controlled oscillator. Connect to pins 2, 4, 6, and 8 of the GO1555. 39145 - 3 November 2007 6 of 26 GS4915 Data Sheet Table 1-1: Pin Descriptions (Continued) Pin Number 36 Name LF Timing Analog Type Output Description Control voltage for the external voltage controlled oscillator. Connect to pin 5 of the GO1555 via a low pass filter. See Typical Application Circuit on page 22. Charge pump current control. Connect to VCO_GND via a 10k resistor. 37 CP_RES Analog Input 38 39 CP_VDD VCO_VDD - - Power Power Power supply for the internal charge pump block (nominally +2.5V DC). Connect to VCO_VDD (pin 39). Power supply for the external voltage controlled oscillator (+2.5V DC). Connect to pin 7 of the GO1555. This pin is an output. Must be isolated from all other power supplies. - Ground Pad - Power Ground pad on bottom of package must be soldered to AGND plane of PCB. 39145 - 3 November 2007 7 of 26 GS4915 Data Sheet 2. Electrical Characteristics 2.1 Absolute Maximum Ratings Parameter Supply Voltage (SE_VDD, REG_VDD) Core Supply Voltage (all 1.8V supplies) Input ESD Voltage Storage Temperature Operating Temperature Value -0.3 to +4.0 VDC -0.3 to +2.2 VDC 1 kV HBM -50C < TS < 125C -20C < TA < 85C NOTE: Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions or at any other condition beyond those indicated in the AC/DC Electrical Characteristic sections is not implied. 2.2 DC Electrical Characteristics Table 2-1: DC Electrical Characteristics VDD = 1.8V 5%, 3.3V 5%; TA = -20C to 85C, unless otherwise shown Parameter Operating Temperature Range Power Consumption (SE_VDD = 1.8V Nominal) Power Consumption (SE_VDD = 3.3V Nominal) +1.8V Power Supply Voltage +3.3V Power Supply Voltage +2.5V Regulator Output Voltage Input Voltage, Logic LOW Input Voltage, Logic HIGH Output Voltage, Logic LOW Output Voltage, Logic HIGH Symbol TA P1.8V Conditions - 1.8V Rail 3.3V Rail Min -20 - - - - 1.71 3.135 2.375 - 0.65 x IO_VDD - 0.65 x IO_VDD 0.65 x IO_VDD Typ 25 156 58 132 133 1.8 3.3 2.5 0 1.8 0 1.8 3.3 Max 85 270 87 243 156 1.89 3.465 2.625 0.35 x IO_VDD - 0.4 - - Units C mW mW mW mW V V V V V V V V Notes - - - - - - - - 1,5 1,5 2,3,5 2,3,5 2,3,5 P3.3V 1.8V Rail 3.3V Rail - - - VIL VIH VOL VOH - - Output load of 3-12mA - - 1.8V or 3.3V operation 1.8V operation 3.3V operation 39145 - 3 November 2007 8 of 26 GS4915 Data Sheet Table 2-1: DC Electrical Characteristics (Continued) VDD = 1.8V 5%, 3.3V 5%; TA = -20C to 85C, unless otherwise shown Parameter Clock Output Drive Current Symbol - Conditions 1.8V operation 3.3V operation Min - - 1.12 240 - Typ 10 8 1.25 350 1.45 Max - - 1.38 460 - Units mA mA V mV V Notes 2,3,4 2,3,4 - - - Differential Input Common Mode Voltage Differential Input Swing Differential Clock Output Common Mode Voltage Differential Clock Output Swing VICM VIDIFF VOCM - - 100 termination between CLKOUT and CLKOUT 100 termination between CLKOUT and CLKOUT VODIFF 250 350 460 mV 6 NOTES: 1. 2. 3. 4. 5. For all LVCMOS compatible inputs. For LVCMOS compatible output SE_CLK. For LVCMOS compatible output LOCK. While still satisfying VOL max and VOH min. IO_VDD refers to the power supply that supplies the particular pin in question. D_VDD supplies pins 10-21. IN_VDD supplies CLKIN_SE. SE_VDD supplies CLKOUT_SE. 6. Differential swing as defined here: CLKOUT VOCM CLKOUT +VODIFF 0V CLKOUT - CLKOUT -VODIFF VODIFF 39145 - 3 November 2007 9 of 26 GS4915 Data Sheet 2.3 AC Electrical Characteristics Table 2-2: AC Electrical Characteristics VDD = 1.8V 5%, TA = 0C to 70C, unless otherwise shown Parameter Input Jitter Tolerance Symbol IJT Conditions < 0.5Hz 0.5Hz to 1Hz 1Hz to 100Hz > 100Hz Min -10 -5 -1 -0.1 - - - - 45 40 - - 12 12 - - - - Typ - - - - 20 40 60 100 - - 500 1200 - - - - - 1.2 Max 10 5 1 0.1 - - - - 55 60 - - 165 165 500 500 1 - Units UI UI UI UI ps ps ps ps % % ps ps MHz MHz us us s ns Notes 1 1 1 1 - - - - - - - - - - - - 2 - Output Jitter Differential Output Output Jitter Single-ended Output Output Duty Cycle - - - - - 100kHz to 10MHz Unfiltered 100kHz to 10MHz Unfiltered Differential output Single-ended output Differential Clock Output Rise / Fall Time Single-ended Clock Output Rise / Fall Time Input Clock Frequency Output Clock Frequency Lock Detect Time Unlock Detect Time Lock Time Device Latency - - - - tLOCKD tUNLOCKD tLOCK - 100 diff. load 10 pF load - - Within 300ppm of reference frequency Within 700ppm of reference frequency - Differential in, Differential out, SKEW_EN = LOW Differential in, Differential out, SKEW_EN = HIGH Single ended in, single ended out, SKEW_EN = LOW Single ended in, single ended out, SKEW_EN = HIGH - 1.2 Tout/4 3.5 - ns - - - ns - - 3.5 Tout/4 750 - ns - Device Latency Difference NOTES: - - - - ps 3 1. One UI refers to one cycle of the input CLK. 2. Assuming power up has already occured. 3. Difference between cleaning and bypass modes. 39145 - 3 November 2007 10 of 26 GS4915 Data Sheet 2.4 Solder Reflow Profiles The device is manufactured with Matte-Sn terminations and is compatible with both standard eutectic and Pb-free solder reflow profiles. The recommended standard eutectic reflow profile is shown in Figure 2-1. MSL qualification was performed using the maximum Pb-free reflow profile shown in Figure 2-2. Temperature 60-150 sec. 10-20 sec. 230C 220C 3C/sec max 183C 6C/sec max 150C 100C 25C Time 120 sec. max 6 min. max Figure 2-1: Standard Eutectic Solder Reflow Profile Temperature 60-150 sec. 20-40 sec. 260C 250C 3C/sec max 217C 6C/sec max 200C 150C 25C Time 60-180 sec. max 8 min. max Figure 2-2: Maximum Pb-Free Solder Reflow Profile (Preferred) 39145 - 3 November 2007 11 of 26 GS4915 Data Sheet 3. Detailed Description 3.1 Functional Overview The GS4915 provides a low jitter clock output when fed with an HD or SD video clock input. Other input clock frequencies between 12MHz and 165MHz can be automatically passed through to the GS4915 outputs. An internal 2:1 mux allows the user to select between a differential (CML/LVDS compatible) or single-ended (LVCMOS) input clock. Both a single-ended LVCMOS-compatible and an LVDS-compatible differential output are provided. The GS4915 may operate in either auto or fixed frequency mode. In auto mode, the device will automatically clean the selected input clock if its frequency is found to be one of the supported SD or HD clock rates. In fixed mode, the user selects only one of these frequencies to be cleaned. In addition, the device allows the user to select between auto or manual bypass operation. In autobypass mode, the GS4915 will automatically bypass its cleaning stage and pass the input clock signal directly to the output whenever the device is unlocked which includes the case where the input frequency is something other than the five frequencies supported. In manual bypass mode, the input signal passes through directly to the output. The GS4915 can optionally double the output frequency for 74.25MHz or 74.175MHz HD clocks in order to provide optimal jitter performance of some serializers. The GS4915 also provides the user with a 2-state skew control. The output clocks produced by the device may be advanced by 1/4 of an output CLK period in order to accommodate downstream setup and hold requirements. The GS4915 is designed to operate with the GO1555 VCO. The GS4915 Clock Cleaner complements Gennum's GS4911B Clock and Timing Generator for implementing a video genlock solution. Whereas the GS4911B itself cleans low-frequency jitter, the GS4915 is designed to clean primarily the higher frequency jitter of clocks generated by the GS4911B. 3.2 Clock Inputs The GS4915 contains two separate input buffers to accept either a differential or single-ended input clock. The applied clock(s) can be any video clock needing cleaning, although typically it will be the video clock specifically used for serialization. The frequency of the applied clock signal(s) must be between 12MHz and 165MHz. The clock input buffers use a separate power supply of +1.8V DC supplied via the IN_VDD pin. 39145 - 3 November 2007 12 of 26 GS4915 Data Sheet 3.2.1 Differential Clock Input A differential LVDS clock signal conforming to the TIA/EIA-644-A standard may be AC-coupled to the CLKIN and CLKIN pins. If the GS4911B/10B/01B/00B is used, the PCLK3 and PCLK3 outputs from that device may be directly connected to the CLKIN and CLKIN inputs of the GS4915, respectively. The CLKIN and CLKIN input traces should be tightly-coupled with a controlled differential impedance of 100. The pair should be terminated with 100 at the input to the device as no internal termination is provided. This input clock is selected as the one to be cleaned by the GS4915 when the IPSEL pin is set LOW. The clock can be DC coupled if the levels are appropriate, but only AC coupling is recommended. These inputs are both LVDS and CML compatible, and AC coupling is only required in cases where the common mode does not line up. 3.2.2 Single-Ended Clock Input A single-ended clock signal at from 1.8V - 3.3V CMOS levels may be DC-coupled to the CLKIN_SE pin. If the GS4911B/10B/01B/00B is used, the PCLK1 or PCLK2 output from that device may be directly connected to the CLKIN_SE input of the GS4915. 3.2.3 Input Clock Selection An internal 2x1 input multiplexer is provided to allow switching between the differential and single-ended clock inputs using one external pin. When IPSEL is set LOW, the differential clock at the CLKIN/CLKIN pins is selected as the one to be processed by the device. When IPSEL is set HIGH, the single-ended clock at the CLKIN_SE pin is selected as the one to be processed. 3.2.4 Unused Clock Inputs If the application will only provide a differential clock input, then the CLKIN_SE input pin should be connected to AGND. If only a single-ended clock will be provided, then the CLKIN/CLKIN pins should be left unconnected. 3.3 Clock Cleaning PLL To obtain a low-jitter output clock signal, the GS4915 uses a clock cleaning phase-locked loop. This block will always attempt to lock an external 1.485GHz VCO signal to the selected input clock. Internal dividers, set by the digital control block based on the frequency mode of the device (see Section 3.4.1), are used to obtain the final output clock of 27MHz (divide by 55), 74.25MHz/74.175MHz (divide by 20), or 148.5MHz/148.35MHz (divide by 10). 39145 - 3 November 2007 13 of 26 GS4915 Data Sheet 3.3.1 Phase Detector The GS4915's phase detector can identify phase misalignment between the selected input clock and the reference clock provided by the external VCO, and correspondingly signal the charge pump to alter the VCO control voltage. 3.3.2 Charge Pump The charge pump block of the PLL is powered externally by +2.5V DC applied to CP_VDD. This is provided by the GS4915 itself at the VCO_VDD pin. An external RC filter at the CP_VDD pin is recommended to reduce supply noise for best jitter performance. Please refer to the Typical Application Circuit on page 22. An external resistance connected to the CP_RES pin is used to set the charge pump reference current of the device. Typically, the CP_RES pin will be connected through 10k to VCO_GND. 3.3.3 Loop Filter The GS4915 PLL loop filter is an external first order filter formed by a series RC connection as shown in Table 3-1: Loop Filter Component Values. The loop filter resistor value sets the bandwidth of the PLL and the capacitor value controls its stability and lock time. A loop filter resistor value between 1 and 20 and a loop filter capacitor value between 1F and 33F are recommended. The GS4915 uses a non-linear, bang-bang, PLL, therefore its bandwidth scales linearly with the input jitter amplitude - greater input jitter results in a smaller loop bandwidth causing more of the input jitter to be rejected. For a given input jitter amplitude, a smaller loop filter resistor produces a narrower loop bandwidth. With an input jitter amplitude of 300ps, for example, the PLL bandwidth can be adjusted from 2KHz to 40KHz by varying the loop filter resistor, as shown in the table below. For use with GS4911, a narrow loop bandwidth is recommended. Increasing the loop filter capacitor value increases the stability of the PLL, but results in a longer lock time. For loop filter resistors smaller than 7, a capacitor value of 33F is recommended, while larger resistor values can accommodate smaller capacitors. Sample combinations of the loop filter resistor and capacitor values are shown in the table below, along with the resulting loop bandwidth. Additional loop bandwidths can be achieved by using different loop filter resistor values. Table 3-1: Loop Filter Component Values Loop Filter R 1 7 20 Typical Loop Bandwidth* 2kHz 8kHz 40kHz Recommended Loop Filter C 33F 10F 1F Wide bandwidth. Fast lock-time. Comments Narrow bandwidth - provides maximum jitter reduction. Long lock-time. Note: 1. *Measured with 300ps pk-pk input jitter on CLK. 39145 - 3 November 2007 14 of 26 GS4915 Data Sheet 3.3.4 External VCO The GS4915 uses the external GO1555 Voltage Controlled Oscillator as part of its phase-locked loop. This external VCO implementation was chosen to ensure superior jitter performance of the device. Power for the external VCO is generated entirely by the GS4915 from an on-chip voltage regulator. The internal regulator uses +3.3V DC supplied at the REG_VDD pin to provide +2.5V at the VCO_VDD pin. Based on the control voltage output by the GS4915 on the LF pin, the GO1555 produces a 1.485GHz reference signal for the PLL. This signal must be run via a 50 controlled-impedance trace to the VCO pin of the GS4915. The VCO receiver block of the device will then convert this single-ended signal into the differential 1.485GHz reference signal used by the clock cleaning PLL. Both the reference and controls signals should be referenced to the supplied VCO_GND, as shown in the recommended application circuit of the Typical Application Circuit on page 22. 3.4 Modes of Operation The GS4915 may operate in one of two possible frequency modes, and in one of three possible bypass modes. The combination of the frequency mode and bypass mode will determine the frequency and jitter of the output clock. 3.4.1 Frequency Modes The frequency mode of the device is determined entirely by the setting of the external FCTRL[1:0] pins. Table 3-2: GS4915 Frequency Modes FCTRL[1:0] 00 01 10 11 Frequency Mode Auto Fixed - 27MHz 0.4% Fixed - 74.25MHz 0.4% Fixed - 148.5MHz 0.4% In both Auto and Fixed Frequency modes, the GS4915 will measure the selected input clock frequency to determine if it is in any of the following ranges: 27MHz 0.4%, 74.25MHz 0.4%, or 148.5MHz 0.4% (these ranges include the 74.25MHz/1.001 and 148.5MHz/1.001 video clock frequencies). 39145 - 3 November 2007 15 of 26 GS4915 Data Sheet Auto Frequency Mode When FCTRL[1:0] = 00, the device will operate in Auto Frequency mode. In this mode, the GS4915 will automatically clean the selected input clock if its frequency is found to be contained in any of the ranges listed above. The LOCK output pin will be HIGH whenever the device has successfully locked its cleaning PLL to the selected input clock. In Auto Frequency mode, LOCK will be HIGH if the input clock frequency is 27MHz 0.4%, 74.25MHz 0.4%, or 148.5MHz 0.4%. If the input clock varies by more than 6.4%, the LOCK output pin will be LOW. Between 0.4% and 6.4%, the device may lock or bypass, as shown in Figure 3-1. Frequencies in this range should not be applied to the device. +6.4% +0.4% -0.4% -6.4% Locked Undefined Unlocked Figure 3-1: Locked, Undefined and Unlocked regions Fixed Frequency Mode When FCTRL[1:0] 00, the device will operate in Fixed Frequency mode. In this mode, the device will only clean the selected input clock if its frequency is found to be in the range defined by the particular setting of the FCTRL[1:0] pins. For example, if FCTRL[1:0] = 01, the GS4915 will only clean the input clock if its frequency is 27MHz 0.4%; if FCTRL[1:0] = 10, the GS4915 will only clean the input clock if its frequency is 74.25MHz 0.4%; and if FCTRL[1:0] = 11, the GS4915 will only clean the input clock if its frequency is 148.5MHz 0.4%. In Fixed Frequency mode, the LOCK output pin will be set HIGH after the device has locked its cleaning PLL to the selected input clock, and only if the input clock frequency matches the frequency selected by the setting of the FCTRL[1:0] pins. Otherwise, LOCK will be LOW. 39145 - 3 November 2007 16 of 26 GS4915 Data Sheet 3.4.2 Bypass Modes The bypass mode of the device is determined by the setting of the external AUTOBYPASS and BYPASS pins. Table 3-3: GS4915 Bypass Modes AUTOBYPASS 0 1 1 NOTE: 'X' indicates a "don't care" condition. BYPASS X 0 1 Bypass Mode Autobypass Mode Forced Output Mode Manual Bypass Mode Autobypass Mode When AUTOBYPASS is LOW, the device will operate in Autobypass mode. In this mode, the GS4915 will bypass its cleaning stage and pass the selected input clock signal directly to the output whenever LOCK is LOW. Manual Bypass Mode When AUTOBYPASS and BYPASS are both HIGH, the GS4915 will operate in Manual Bypass Mode. In this mode, the GS4915 will bypass its cleaning stage and pass the selected input clock signal directly to the output. NOTE: If operating in Manual Bypass mode, the LOCK output pin should be ignored. Depending on the set frequency mode of the device and the detected frequency of the selected input clock, the cleaning PLL of the device may achieve lock and so may set the LOCK pin HIGH; however, the output clock will always be a copy of the input clock, and NOT the cleaned clock. Forced Output Mode If AUTOBYPASS is HIGH and BYPASS is set LOW, the device will operate in Forced Output mode. In this mode, the cleaning stage of the device is never bypassed, and so the output clock will always be the clock output by the device's PLL, even in an unlocked condition. When LOCK is HIGH, the output clock will be low-jitter and locked to the selected input clock. But when LOCK is LOW in Forced Output mode, the output clock should not be used. 39145 - 3 November 2007 17 of 26 GS4915 Data Sheet 3.5 Output Clock Frequency and Jitter The frequency and jitter of the output clock are determined by: * * * * * the frequency of the input clock, the differential or single-ended input and output clocks, the selected frequency mode, the selected bypass mode, and the setting of the DOUBLE pin. When the DOUBLE pin is set HIGH, the output clock frequency will be double the input only when the selected input clock frequency is determined to be 74.25MHz 0.4%. Otherwise, the setting of the DOUBLE pin will have no effect on the frequency of the output clock. The output clock will be low jitter when the LOCK pin is HIGH. The only exception to this is if operating in Manual Bypass mode, see Section 3.4.2.Table 3-4, Table 3-5, and Table 3-6 summarize the output frequency and LOCK behaviour of the device given the frequency of the input clock, the selected frequency mode, and the setting of the DOUBLE pin for Autobypass, Manual Bypass, and Forced Output modes, respectively. In each table, 'X' indicates a "don't care" condition. Table 3-4: Output Behaviour in Autobypass Mode FCTRL[1:0] Auto [00] Input 27MHz 74.25MHz DOUBLE X 0 1 LOCK HIGH HIGH HIGH HIGH LOW HIGH LOW LOW LOW LOW HIGH HIGH LOW LOW LOW LOW HIGH LOW Output 27MHz 74.25MHz 148.5MHz 148.5MHz Input 27MHz 74.25MHz 148.5MHz Input 27MHz 74.25MHz 148.5MHz 148.5MHz Input 27MHz 74.25MHz 148.5MHz Input 148.5MHz Other Fixed - 27MHz [01] 27MHz 74.25MHz 148.5MHz Other Fixed - 74.25MHz [10] 27MHz 74.25MHz X X X X X X X 0 1 148.5MHz Other Fixed - 148.5MHz [11] 27MHz 74.25MHz 148.5MHz Other X X X X X X 39145 - 3 November 2007 18 of 26 GS4915 Data Sheet Table 3-5: Output Behaviour in Manual Bypass Mode FCTRL[1:0] Auto [00] Input 27MHz 74.25MHz 148.5MHz Other DOUBLE X X X X X X X X 0 0 0 0 X X X X LOCK HIGH* HIGH* HIGH* LOW HIGH* LOW LOW LOW LOW HIGH* LOW LOW LOW LOW HIGH* LOW Output 27MHz 74.25MHz 148.5MHz Input 27MHz 74.25MHz 148.5MHz Input 27MHz 74.25MHz 148.5MHz Input 27MHz 74.25MHz 148.5MHz Input Fixed - 27MHz [01] 27MHz 74.25MHz 148.5MHz Other Fixed - 74.25MHz [10] 27MHz 74.25MHz 148.5MHz Other Fixed - 148.5MHz [11] 27MHz 74.25MHz 148.5MHz Other *NOTE: Although LOCK = HIGH under these conditions, the output clock will be a copy of the selected input clock and will have the jitter of the input clock. Table 3-6: Output Behaviour in Forced Output Mode FCTRL[1:0] Auto [00] Input 27MHz 74.25MHz DOUBLE X 0 1 LOCK HIGH HIGH HIGH HIGH LOW HIGH LOW LOW LOW Output 27MHz 74.25MHz 148.5MHz 148.5MHz Last locked* 27MHz 27MHz 27MHz 27MHz 148.5MHz Other Fixed - 27MHz [01] 27MHz 74.25MHz 148.5MHz Other X X X X X X 39145 - 3 November 2007 19 of 26 GS4915 Data Sheet Table 3-6: Output Behaviour in Forced Output Mode (Continued) FCTRL[1:0] Fixed - 74.25MHz [10] Input 27MHz DOUBLE 0 1 LOCK LOW LOW HIGH HIGH LOW LOW LOW LOW LOW LOW HIGH LOW Output 74.25MHz 148.5MHz 74.25MHz 148.5MHz 74.25MHz 148.5MHz 74.25MHz 148.5MHz 148.5MHz 148.5MHz 148.5MHz 148.5MHz 74.25MHz 0 1 148.5MHz 0 1 Other 0 1 Fixed - 148.5MHz [11] 27MHz 74.25MHz 148.5MHz Other X X X X *NOTE: The output clock will remain within 5% of the last locked frequency if an input frequency other than 27MHz, 74.25MHz, or 148.5MHz is applied to the selected clock input. If operating under these conditions upon power-up, the output frequency will be 74.25MHz 5%. 3.6 Output Skew The GS4915 provides the user with the option of advancing the phase of the output clock from that of the input clock. This feature is controlled by the external SKEW_EN pin. When SKEW_EN is set LOW, the output clock will be delayed from the selected input clock only by the latency of the device. By setting SKEW_EN = HIGH, the user can advance the output clock from the selected input clock by one quarter of an output period, minus the latency of the device. Please see Figure 3-2. Input Clock Output Clock Device Latency 1/4 CLK Period - Device Latency SKEW_EN = LOW SKEW_EN = HIGH Figure 3-2: Output skew behaviour of GS4915 39145 - 3 November 2007 20 of 26 GS4915 Data Sheet 3.7 Clock Outputs The GS4915 presents both differential and single-ended clock outputs. When the LOCK output signal is HIGH, these clock outputs will be low-jitter and locked to the selected input clock. NOTE: If in Manual Bypass mode, the LOCK pin may be HIGH although the output clock will always be a copy of the input clock, and NOT the cleaned clock. The frequency of the differential and single-ended clock outputs will be identical and will be determined as described in Section 3.5. 3.7.1 Differential Clock Output A CML-based driver is used to provide the differential clock output at the CLKOUT and CLKOUT pins. Although this driver will output a signal amplitude that is compatible to the TIA/EIA-644 LVDS standard, it has an incompatible common mode level. Therefore, AC-coupling and external biasing resistors are required if interfacing the differential clock outputs from the GS4915 to a true LVDS receiver. The common mode is, however, compatible with the LVDS inputs on most FPGAs and can be DC coupled. This is the lowest-jitter output of the GS4915. The differential clock output driver uses a separate power supply of +1.8V DC supplied via the DIFF_OUT_VDD pin. 3.7.2 Single-Ended Clock Output The single-ended output clock is present at the CLKOUT_SE pin. The signal will operate at either 1.8V or 3.3V CMOS levels, as determined by the voltage applied to the D_VDD pin. The single-ended clock output pre-drive uses a separate power supply of +1.8V DC supplied via the SE_VDD pin. 3.8 Device Reset 3.8.1 Hardware Reset In order to reset the GS4915 to their defaults conditions, the RESET pin must be held LOW for a minimum of treset = 0.5ms. 39145 - 3 November 2007 21 of 26 GS4915 Data Sheet 4. Typical Application Circuit 1.8V_A 1.8V_A 1.8V_D 1.8V_D 3.3V 3.3V VCO_VDD C1 10n AGND 1.8V_A C13 0.1u C14 0.1u DGND2 1.8V_D C15 0.1u C16 0.1u C17 0.1u C18 0.1u AGND 3.3V C11 0.1u C12 0.1u VCO_VDD R16 150K *Refer to Table 3-1 in Section 3.3.3 for R & C Loop Filter component values. 7 6 5 GND C19 10u C22 10u C28 10u 8 VCC O/P 1 2 3 GND GO1555 GND VCTR NC AGND Pin 3 AGND Pin 32 AGND Pin 7 DGND2 Pin 25 AGND Pin 27 DGND2 Pin 15 AGND Pin 1 AGND Pin 23 C2* VCO_GND VCO_GND VCO_GND Controlled impedance 50-ohms VCO_VDD C10 0.1u 1u VCO_GND VCO_GND C6 10n R5 10K 1.8V_A 37 35 34 39 33 40 32 U2 AGND 38 36 31 AGND VCO_GND VCO_VDD 3.3V 1 2 DIV_VDD CP_VDD CP_RES AGND VCO VCO LF AGND REG_VDD AGND PD_VDD CLKIN CLKIN AGND IN_VDD CLKIN_SE AGND AGND CLKOUT CLKOUT DIFF_OUT_VDD AGND 30 29 28 27 26 25 24 23 22 21 LOCK 3.3V 1.8V_D 4 R15 150K R1* U1 GND GO1525 PCLK Zo = 100 ohms differential PCLK I.8V_D PCLKIN Zo = 100 ohms differential PCLKIN R6 100R 1.8V_A 3 4 5 6 GS4915 D_VDD CLKOUT_SE SE_VDD GND 1.8V_D 7 8 9 10 PCLK_SE PCLKIN_SE AUTOBYPASS RESET GND_PAD LOCK SKEW_EN 19 DOUBLE FCTRL0 FCTRL1 BYPASS D_VDD IPSEL GND 11 12 13 14 15 16 17 18 RESET R8 0R IPSEL BY PASS MAN/AUTOb CTRL0 CTRL1 DOUBLE SKEW_EN 1.8V_D DGND2 DGND2 20 AGND GND VCO_GND AGND Figure 4-1: GS4915 Typical Application Circuit 39145 - 3 November 2007 22 of 26 GS4915 Data Sheet 5. References & Relevant Standards Table 5-1: References & Relevant Standards EIA/JEDEC JESD8-B EIA/JEDEC JESD8-7 TIA/EIA-644-A SMPTE 240M-1999 SMPTE 259M-1997 SMPTE 274M-1998 SMPTE 292M-1998 SMPTE 294M-1997 SMPTE 295M-1997 SMPTE 296M-1997 SMPTE RP 184-2004 SMPTE RP 211-2000 ITU-R BT.656 ITU-R BT.709-4 Interface standard for 3V/3.3V Supply Digital Integrated Circuits Interface standard for 1.8-V Supply Digital Integrated Circuits Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface Circuits 1125-Line High Definition Production Systems - Signal Parameters 10-bit 4:2:2 Component and 4fsc Composite Digital Signals Serial Digital Interface 1920 x 1080 Scanning and Analog and Parallel Digital Interfaces for Multiple Picture Rates Bit-Serial Digital Interface for High-Definition Television Systems 720 x 483 Active Line at 59.94-Hz Progressive Scan Production - Bit-Serial Interfaces 1920 x 1080 50 Hz - Scanning and Interfaces 1280 x 720 Scanning, Analog and Digital Representation and Analog Interface Specification of Jitter in Bit-Serial Digital Systems Implementation of 24P, 25P and 30P Segmented Frames for 1920 x 1080 Production Format Interface for Digital Component Video Signals in 525-Line and 625-Line Television Systems Parameter Values for the HDTV Standards for Production and International Program Exchange 39145 - 3 November 2007 23 of 26 GS4915 Data Sheet 6. Package & Ordering Information 6.1 Package Dimensions 6.00 PIN 1 MARKING AREA A B 4.450.05 DATUM A 0.50 6.00 DETAIL B 451 DATUM B 2X 0.15 C Top View 0.310.05 Bottom View 40X 0.230.05 0.10 M 0.05 M CAB C 2X 0.15 C 0.10 C 40X C 0.02 +0.03 - 0.03 0.900.10 DATUM A OR B 0.50/2 0.50 DETAIL B TERMINAL TIP 39145 - 3 November 2007 0.20 REF 0.08 C SEATING PLANE 24 of 26 4.450.05 0.30@45 CHAMFER 0.500.05 GS4915 Data Sheet 6.2 Recommended PCB Footprint 0.50 0.25 0.65 5.60 4.45 CENTER PAD 4.45 5.60 NOTE: All dimensions are in millimeters. NOTE: Suggested dimensions only. Final dimensions should conform to customer design rules 1 and process optimizations. 6.3 Packaging Data Parameter Package Type Moisture Sensitivity Level Junction to Case Thermal Resistance, j-c Junction to Air Thermal Resistance, j-a (at zero airflow) Junction to Board Thermal Resistance, j-b Psi, Pb-free and RoHS Compliant Value 6mm x 6mm 40-pin QFN 3 19.9C/W 34.9C/W 12.5C/W 0.5C/W Yes 6.4 Ordering Information Part Number GS4915-INE3 Package Pb-free 40-pin QFN Temperature Range -20C to 85C 39145 - 3 November 2007 25 of 26 GS4915 Data Sheet 7. Revision History Version 0 ECR 142746 PCN - Date November 2006 Changes and/or Modifications Converting to Preliminary Data Sheet. Removed `Proprietary and Confidential' footer. Modified Table 1-1: Pin Descriptions. Updated DC Electrical Characteristics and AC Electrical Characteristics table. Modified Typical Application Circuit. Added junction - board thermal resistance parameter to section 6.3 Packaging Data. Corrected pin 38 (CP_VDD) connection on Typical Application Circuit. Defined IO_VDD see Note 5 in 2.2 DC Electrical Characteristics and added chamfer dimensions in 6.2 Recommended PCB Footprint. Added pin descriptions for D-VDD, IN_VDD and SEto 1.2 Pin Descriptions. Changed Loop Bandwidth to 2kHz in Key Features. Added section 3.3.3 Loop Filter and Table 3-1: Loop Filter Component Values. Changed some pin descriptions. Updated power consumption values in Table 2-1: DC Electrical Characteristics. Converted document to Data Sheet. Updated Power Consumption values in Table 2-1: DC Electrical Characteristics. 1 2 144087 145306 43245 - February 2007 August 2007 3 146729 - November 2007 CAUTION ELECTROSTATIC SENSITIVE DEVICES DO NOT OPEN PACKAGES OR HANDLE EXCEPT AT A STATIC-FREE WORKSTATION DOCUMENT IDENTIFICATION DATA SHEET The product is in production. Gennum reserves the right to make changes to the product at any time without notice to improve reliability, function or design, in order to provide the best product possible. GENNUM CORPORATION Mailing Address: P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3 Shipping Address: 970 Fraser Drive, Burlington, Ontario, Canada L7L 5P5 Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 GENNUM JAPAN CORPORATION Shinjuku Green Tower Building 27F, 6-14-1, Nishi Shinjuku, Shinjuku-ku, Tokyo, 160-0023 Japan Tel. +81 (03) 3349-5501, Fax. +81 (03) 3349-5505 GENNUM UK LIMITED 25 Long Garden Walk, Farnham, Surrey, England GU9 7HX Tel. +44 (0)1252 747 000 Fax +44 (0)1252 726 523 Gennum Corporation assumes no liability for any errors or omissions in this document, or for the use of the circuits or devices described herein. The sale of the circuit or device described herein does not imply any patent license, and Gennum makes no representation that the circuit or device is free from patent infringement. GENNUM and the G logo are registered trademarks of Gennum Corporation. (c) Copyright 2006 Gennum Corporation. All rights reserved. Printed in Canada. www.gennum.com 39145 - 3 November 2007 26 26 of 26 |
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